Scalable Hardware Verification with Symbolic Simulation:

Scalable Hardware Verification with Symbolic Simulation

Product Description

Scalable Hardware Verification with Symbolic Simulation presents recent advancements in symbolic simulation-based solutions which radically improve scalability. It overviews current verification techniques, both based on logic simulation and formal verification methods, and unveils the inner workings of symbolic simulation. The core of this book focuses on new techniques that narrow the performance gap between the complexity of digital systems and the limited ability to verify them. In particular, it covers a range of solutions that exploit approximation and parametrization methods, including quasi-symbolic simulation, cycle-based symbolic simulation, and parameterizations based on disjoint-support decompositions. In structuring this book, the author’s hope was to provide interesting reading for a broad range of design automation readers. The first two chapters provide an overview of digital systems design and, in particular, verification. Chapter 3 reviews mainstream symbolic techniques in formal verification, dedicating most of its focus to symbolic simulation. The fourth chapter covers the necessary principles of parametric forms and disjoint-support decompositions. Chapters 5 and 6 focus on recent symbolic simulation techniques, and the final chapter addresses key topics needing further research. Scalable Hardware Verification with Symbolic Simulation is for verification engineers and researchers in the design automation field. Highlights: A discussion of the leading hardware verification techniques, including simulation and formal verification solutions Important concepts related to the underlying models and algorithms employed in the field The latest innovations in the area of symbolic simulation, exploiting techniques such as parametric forms and decomposition properties of Boolean functions Providing insights into possible new developments in the hardware verification

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Co-verification of Hardware and Software for ARM SoC Design (Embedded Technology): Jason Andrews:

Posted by Hume under General Programming

Co-verification of Hardware and Software for ARM SoC Design (Embedded Technology): Jason Andrews
Newnes | ISBN: 0750677309 | 2004-08-16 | PDF (OCR) | 288 pages | 1.76 Mb

Hardware/software co-verification is how to make sure that embedded system software works correctly with the hardware, and that the hardware has been properly designed to run the software successfully -before large sums are spent on prototypes or manufacturing.
This is the first book to apply this verification technique to the rapidly growing field of embedded systems-on-a-chip(SoC). As traditional embedded system design evolves into single-chip design, embedded engineers must be armed with the necessary information to make educated decisions about which tools and methodology to deploy. SoC verification requires a mix of expertise from the disciplines of microprocessor and computer architecture, logic design and simulation, and C and Assembly language embedded software. Until now, the relevant information on how it all fits together has not been available. Andrews, a recognized expert, provides in-depth information about how co-verification really works, how to be successful using it, and pitfalls to avoid. He illustrates these concepts using concrete examples with the ARM core – a technology that has the dominant market share in embedded system product design. The companion CD-ROM contains all source code used in the design examples, a searchable e-book version, and useful design tools.
* The only book on verification for systems-on-a-chip (SoC) on the market
* Will save engineers and their companies time and money by showing them how to speed up the testing process, while still avoidingcostly mistakes
* Design examples use the ARM core, the dominant technology in SoC, and all the source code is included on the accompanying CD-Rom, so engineers can easily use it in their own designs
Download Description:
Hardware/software co-verification is how to make sure that embedded system software works correctly with the hardware, and that the hardware has been properly designed to run the software successfully -before large sums are spent on prototypes or manufacturing. This is the first book to apply this verification technique to the rapidly growing field of embedded systems-on-a-chip(SoC). As traditional embedded system design evolves into single-chip design, embedded engineers must be armed with the necessary information to make educated decisions about which tools and methodology to deploy. SoC verification requires a mix of expertise from the disciplines of microprocessor and computer architecture, logic design and simulation, and C and Assembly language embedded software. Until now, the relevant information on how it all fits together has not been available.
Table of Contents
Ch. 1 Embedded system verification : an introduction 1
Ch. 2 Hardware and software design process 25
Ch. 3 SoC verification topics for the ARM architecture 69
Ch. 4 Hardware/software co-verification 119
Ch. 5 Advanced hardware/software co-verification 165
Ch. 6 Hardware verification environment and co-verification 197
Ch. 7 Methodology for an example ARM SoC 229

Jason Andrews’ book is one of the nicest, smooth-flowing books I have read recently.

I often avoid reading technical books, since they do not flow at all! Jason has made system verification come out alive and easy for people like me using scores of practical real-life examples. It is very helpful for chip designers and verification engineers/executives like me who are slowly moving up the food chain to system-level for SoC development and design re-use.

What’s more — the book is a lot more reasonably than many others on similar topics! I bought my copy at almost a third of the price I have paid for similar books!
-Shankar@Hemmady.com

Founder, Guru Technologies. Chip verification consultant/manager at Fujitsu, HP, Intel, Xerox, and twelve other companies since the 1990s

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